(1) Field of the Invention
The present invention relates to a semiconductor device. More particularly, it relates to an ohmic contact structure for connecting an electrode to a highly integrated semiconductor device and a method for making the ohmic contact structure.
(2) Description of the Prior Art
The degree of high density integrated circuits has been doubling year after year. Presently, mass production of 16 M dynamic random access memory devices has begun using a sub-half micron design rule. The performance speed of these devices is improved over its predecessors, but a resistance-capacitance delay and characteristics of lines are degraded due to the microminiaturization of the lines with the increased integration and with the increased length of the lines. Accordingly, a technique of forming a contact hole in the devices using sub-half micron design rules is important, particularly with respect to the desired goals of low resistance and high reliability of the semiconductor devices.
An electrode is generally connected to a semiconductor device through a contact hole formed on an insulating layer such as a silica glass or a borophosphorous silicate glass. The junction formed between the metal layer and the semiconductor through the contact hole is characterized as a rectifying contact and a non-rectifying contact as first proposed by Shottky in 1940. A non-rectifying contact is theoretically formed in either of the following two cases: First, when the work function of a metal material is smaller than the work function of a semiconductor material in an n-type semiconductor substrate, and second when the work function of a metal material is larger than the work function of a semiconductor substrate in a p-type semiconductor substrate.
An ideal Shottky contact is too difficult to form using today's technology, i.e., to achieve a contact between a metal and a semiconductor with a resistance near zero. U.S. Pat. No. 4,738,937 describes this theory.
U.S. Pat. No. 5,108,954 describes one prior art technique for forming a contact hole to lower the contact resistance as shown in FIG. 1.
FIG. 1 shows a junction region 3 of a semiconductor substrate 1 and in which impurities are implanted. An insulating layer 5 is deposited on a surface of the semiconductor substrate 1 and junction region 3 with a contact hole formed therein above the junction region 3. A diffusion prevention layer 7 of titanium nitride (TIN) or titanium tungstenite (TiW) is formed on the insulating layer 5 and in the contact hole and over the exposed portion of the junction region 3 so as to prevent metal or silicon electromigration resulting from a diffusion of metal and silicon between the semiconductor substrate 1 and a metal layer 9 forming a wiring electrode deposited on the diffusion prevention layer 7. If the metal layer 9 has considerable thickness, it is formed from the bottom of the contact hole to the surface of the insulating layer 5 along sidewalls of the contact hole, thus forming an electrical contact between the semiconductor substrate and the wiring electrode 9.
When a subsequent thermal treatment is performed, i.e., when silicide TiSi.sub.2 is formed by a heat treatment of titanium and silicon, out-diffusion occurs causing a sharp drop in the concentration of the dopant in the interface of the diffusion-prevention layer 7. This increases the contact resistance. The relationship between the contact resistance and the dopant concentration will now be described.
A plug implantation technique of additionally ion-implanting the dopant after the contact hole is formed so as to prevent the out-diffusion of the dopant and supplement the reduced dose is known. FIG. 2 shows a plug implantation technique wherein a protrusion 3a is formed under the junction region 3 adjacent to the contact hole. This protrusion 3a does not cause a serious problem in the conventional semiconductor device having a relatively deep junction in a substrate. However, as in the case of a very large scale integrated circuit (VLSI) in which a large number of devices are assembled in a unit area, this protrusion 3a may cause short-circuit conductivity in a semiconductor device having a shallow junction. Thus, this design is disadvantageous in improving performance speed in VLSI devices. Moreover, because the impurity level exceeds the solubility limit in a junction area, the junction area is saturated with the impurity and a deposit of the doped impurity is shown as a separate phase.
Therefore, the impurity level in the junction area is limited. If the deposit is shown in the junction region, an increase of the dose of the impurity cannot further increase carrier density. Furthermore, the deposits into many silicon grains cause a diffusion of the carriers and facilitates reunion of the carriers.